1. Field of the Present Invention
The present invention relates generally to the field of circuit design, and more specifically to the field of integrated circuits requiring radiation hardness.
2. History of the Related Art
In order to minimize active power dissipation in integrated circuits (ICs), it is common for engineers to scale the power-supply voltage VDD. For any given circuit activity factor, α, the power savings attributed to power scaling are attributable to the following relationship in Equation (1):Pactive=αCVDD2F.  (1)Process scaling, which reduces VDD to maintain relatively constant device electric fields, has provided most of the power savings in modern very large scale integrated (VSLI) circuits. However, as die size and integration have increased, overall power consumption has risen dramatically. As such, even more innovation has been directed at the reduction in VDD for numerous types of circuits, especially for portable electronics having battery supplies such as those found in notebook computers, mobile telephones, and the like.
Lower power consumption is also useful in other types of circuits that are used in space applications, where power and thermal capacity are strictly limited. Additionally, lower power consumption translates directly into reductions in weight and costs, both of which are important for space-based applications. Unlike most terrestrial applications, however, space-based circuits are much more likely to be exposed to ionizing radiation, such as from a heavy ion or proton. Ionizing radiation can cause single event upsets (SEU), which introduce undesirable current into the IC. The added current is in turn responsible for single event effects (SEE), which can affect the performance and durability of the IC.
One suitable solution to mitigate both SEU and SEE is to harden the IC, which can include for example various elements or methods for attenuating or mitigating the effects of the additional current resulting from the ionizing radiation. These may include fabrication on a silicon on insulator (SOI) technology, which limits charge collection from ionizing radiation. For example, FIG. 1 illustrates a radiation hardened SRAM cell 1 that includes a first gate 2 and a second gate 3. A pair of resistors 4, 5 function to isolate the gates 2, 3 from the drain junctions, thus inserting an RC delay between the collection point and the feedback point of the circuit. With the additional RC delay, the voltage transient due to any incident radiation is attenuated by the resistors 4, 5 prior to causing any feedback to affect the logic and/or memory of the cell 1.
FIG. 2 illustrates another example circuit that is a master-slave flip-flop (MSFF) 7 that uses a pair of resistors 8, 9 in the feedback loops to provide SEE immunity. In this design, the SEE immunity is due to the fact that the latch entrance node has a high capacitance and sufficient drive to absorb any SEU-generated charge at that node. Unfortunately, however, the introduction of the resistors to harden the circuit also increases the master and slave latch setup times tsetup proportionally to the RC time constant. There is an entire clock phase to write the slave latch as in any conventional MSFF, which, without careful design, can impact on the clock to output time (tCLK2Q).
FIG. 3 shows the results of four test cases designed to expose the SET immunity of the circuit shown in FIG. 2. The test cases involved four different inputs into the circuit ([1]0→1, [2]1→0, [3]0→0, and [4]1→1), and as shown in FIG. 3, an SET is absorbed on the clock node before upsetting the latch state and can have a negative effect in increasing the hold time of the circuit. Moreover, an SEU can cause one node of the storage element, i.e. master or slave component, to swing in the opposite direction of the data, which also increases the setup and hold times of the circuit.
Prior attempts to harden ICs have resulted in either slower performance as measured by increased setup and/or hold times, or conversely in increased power consumption in order to immunize the latch elements from SEU and single event transients (SET). Therefore, there is a need in the art for a circuit design that provides the benefits of flexible and reduced power consumption while simultaneously protecting the circuit against SEE, SEU and SET. Such a novel and useful circuit would have numerous potential applications, and would find particular use in space-based applications in which a circuit combining lower power consumption and radiation hardness is most desired.